2852 search results - page 172 / 571 » High Performance Architectures and Compilers |
135
Voted
ICS
1999
Tsinghua U.
15 years 7 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
133
Voted
DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
135
Voted
PPOPP
2009
ACM
16 years 4 months ago
2009
ACM
Understanding why the performance of a multithreaded program does not improve linearly with the number of cores in a sharedmemory node populated with one or more multicore process...
138
Voted
DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
Coarse-grained reconfigurable architectures aim to achieve both goals of high performance and flexibility. However, existing reconfigurable array architectures require many resour...
125
click to vote
APCSAC
2000
IEEE
15 years 8 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...