2852 search results - page 175 / 571 » High Performance Architectures and Compilers |
109
Voted
HPCC
2007
Springer
15 years 9 months ago
2007
Springer
This paper presents a new algorithm for computing the singular value decomposition (SVD) on multilevel memory hierarchy architectures. This algorithm is based on one-sided JRS iter...
120
Voted
GLVLSI
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
140
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IPPS
2000
IEEE
15 years 8 months ago
2000
IEEE
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
118
Voted
ICIAP
2009
ACM
16 years 4 months ago
2009
ACM
In this paper we present an overview of the historical evolution of connected component labeling algorithms, and in particular the ones applied on images stored in raster scan orde...
101
Voted
FPL
2008
Springer
15 years 5 months ago
2008
Springer
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...