2852 search results - page 187 / 571 » High Performance Architectures and Compilers |
149
Voted
FPL
2004
Springer
15 years 9 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
143
Voted
DAC
2001
ACM
16 years 4 months ago
2001
ACM
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
131
click to vote
BSN
2009
IEEE
15 years 10 months ago
2009
IEEE
Wireless systems that form a body-area network must be made small and low power without sacrificing performance. To achieve high-throughput communication in low-cost wireless bod...
166
Voted
CCGRID
2005
IEEE
15 years 9 months ago
2005
IEEE
In this article we present the design choices and the evaluation of a batch scheduler for large clusters, named OAR. This batch scheduler is based upon an original design that emp...
113
click to vote
ACSAC
2000
IEEE
15 years 8 months ago
2000
IEEE
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...