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ISCAPDCS
2004
15 years 5 months ago
A New Multicast Queuing Mechanism for High-Speed Packet Switches
Increasing multimedia applications such as teleconferencing and video-on-demand require the Internet to effectively provide high-performance multicast support. One of the promisin...
Min Song, Sachin Shetty, Mansoor Alam, HouJun Yang
133
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CORR
2006
Springer
116views Education» more  CORR 2006»
15 years 3 months ago
Memory Aware High-Level Synthesis for Embedded Systems
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
Gwenolé Corre, Eric Senn, Nathalie Julien, ...
119
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FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 9 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
133
Voted
TVLSI
2008
120views more  TVLSI 2008»
15 years 3 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
15 years 9 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...