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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 9 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
ICWS
2010
IEEE
15 years 5 months ago
Highly Scalable Web Service Composition Using Binary Tree-Based Parallelization
Data intensive applications, e.g. in life sciences, pose new efficiency challenges to the service composition problem. Since today computing power is mainly increased by multiplica...
Patrick Hennig, Wolf-Tilo Balke
118
Voted
AHS
2007
IEEE
215views Hardware» more  AHS 2007»
15 years 3 months ago
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
118
Voted
ISCAS
2006
IEEE
113views Hardware» more  ISCAS 2006»
15 years 9 months ago
High speed routing lookup IC design for IPv6
— With the growth of Internet users and services, the IP address has been exhausted. In order to solve this problem, the short term solution was presented, i.e., CIDR (Classless ...
Yuan-Sun Chu, Hui-Kai Su, Po-Feng Lin, Ming-Jen Ch...
126
Voted
FPL
2006
Springer
96views Hardware» more  FPL 2006»
15 years 7 months ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...