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102
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ISVLSI
2005
IEEE
80views VLSI» more  ISVLSI 2005»
15 years 9 months ago
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
Renqiu Huang, Ranga Vemuri
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
15 years 9 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
129
Voted
ISPASS
2006
IEEE
15 years 9 months ago
Critical path analysis of the TRIPS architecture
Fast, accurate, and effective performance analysis is essential for the design of modern processor architectures and improving application performance. Recent trends toward highly...
Ramadass Nagarajan, Xia Chen, Robert G. McDonald, ...
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 7 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
121
Voted
VSTTE
2005
Springer
15 years 9 months ago
Verifying Design with Proof Scores
: Verifying design instead of code can be an effective and practical approach to obtaining verified software. This paper argues that proof scores are an attractive method for ver...
Kokichi Futatsugi, Joseph A. Goguen, Kazuhiro Ogat...