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» High Performance Architectures and Compilers
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119
Voted
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
15 years 9 months ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
125
Voted
ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
15 years 7 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...
159
Voted
CSMR
2002
IEEE
15 years 8 months ago
Reengineering to the Web: A Reference Architecture
Reengineering existing (large-scale) applications to the web is a complex and highly challenging task. This is due to a variety of mostly demanding requirements for interactive we...
Uwe Zdun
100
Voted
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
15 years 9 months ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
261
Voted
POPL
2007
ACM
16 years 3 months ago
A concurrent constraint handling rules implementation in Haskell with software transactional memory
Constraint Handling Rules (CHR) is a concurrent committedchoice constraint logic programming language to describe transformations (rewritings) among multi-sets of constraints (ato...
Edmund S. L. Lam, Martin Sulzmann