6 search results - page 1 / 2 » High Performance Architectures and Compilers |
154
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ISVLSI
2005
IEEE
15 years 7 months ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
111
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ISVLSI
2005
IEEE
15 years 7 months ago
2005
IEEE
The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique...
ISVLSI
2005
IEEE
15 years 7 months ago
2005
IEEE
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
125
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ISVLSI
2002
IEEE
15 years 6 months ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
115
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ISVLSI
2008
IEEE
15 years 7 months ago
2008
IEEE
Scalability of architecture, programming model and task control management will be a major challenge for future VLSI systems. In this context, homogeneous MPSOC is a seducing appr...