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IEEEPACT
2007
IEEE
15 years 10 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
IWAN
2001
Springer
15 years 8 months ago
Deploying an Active Voice Application on a Three-Level Active Network Node Architecture
Active networks have been recently highlighted as a key enabling technology to obtain immense flexibility in terms of network deployment, configurability, and customized packet pro...
Georg Carle, Henning Sanneck, Sebastian Zander, Lo...
173
Voted
DAC
2006
ACM
16 years 4 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 8 months ago
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
This paper presents ReVive, a novel general-purpose rollback recovery mechanism for shared-memory multiprocessors. ReVive carefully balances the conflicting requirements of avail...
Milos Prvulovic, Josep Torrellas, Zheng Zhang
123
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ICNP
1998
IEEE
15 years 7 months ago
Distributed Packet Rewriting and its Application to Scalable Server Architectures
To construct high performance Web servers, system builders are increasingly turning to distributed designs. An important challenge that arises in such designs is the need to direc...
Azer Bestavros, Mark Crovella, Jun Liu, David Mart...