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142
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CASES
2007
ACM
15 years 7 months ago
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
117
Voted
DAC
1998
ACM
16 years 4 months ago
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs
In this paper we present a new global router appropriate for Multichip Module MCM and dense Printed Circuit Board PCB design, which utilizes a hybrid of the classical rip-up and r...
Jason Cong, Patrick H. Madden
143
Voted
ACMACE
2009
ACM
15 years 1 months ago
Dramaturgies of PLACE: evaluation, embodiment and performance in PLACE-Hampi
This paper examines an extensive user evaluation survey undertaken during an installation of PLACE-Hampi, a custombuilt augmented stereoscopic panoramic interactive cultural herit...
Sarah Kenderdine, Jeffrey Shaw, Anita Kocsis
VLSI
2007
Springer
15 years 9 months ago
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
— In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. Industry trends indicate that such coproc...
Pranav Vaidya, Jaehwan John Lee
134
Voted
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 7 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...