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» High Performance Architectures and Compilers
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129
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IPPS
2006
IEEE
15 years 9 months ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
190
Voted
LCPC
2009
Springer
15 years 8 months ago
MIMD Interpretation on a GPU
Programming heterogeneous parallel computer systems is notoriously difficult, but MIMD models have proven to be portable across multi-core processors, clusters, and massively paral...
Henry G. Dietz, B. Dalton Young
155
Voted
FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 7 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
157
Voted
ASPLOS
2006
ACM
15 years 9 months ago
Combinatorial sketching for finite programs
Sketching is a software synthesis approach where the programmer develops a partial implementation — a sketch — and a separate specification of the desired functionality. The ...
Armando Solar-Lezama, Liviu Tancau, Rastislav Bod&...
139
Voted
ISHPC
2000
Springer
15 years 7 months ago
Leveraging Transparent Data Distribution in OpenMP via User-Level Dynamic Page Migration
This paper describes transparent mechanisms for emulating some of the data distribution facilities offered by traditional data-parallel programming models, such as High Performance...
Dimitrios S. Nikolopoulos, Theodore S. Papatheodor...