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134
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FPL
2005
Springer
127views Hardware» more  FPL 2005»
15 years 9 months ago
Efficient Hardware Architectures for Modular Multiplication on FPGAs
The computational fundament of most public-key cryptosystems is the modular multiplication. Improving the efficiency of the modular multiplication is directly associated with the...
David Narh Amanor, Viktor Bunimov, Christof Paar, ...
132
Voted
IPPS
1996
IEEE
15 years 7 months ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...
142
Voted
IPPS
2008
IEEE
15 years 10 months ago
A plug-and-play model for evaluating wavefront computations on parallel architectures
This paper develops a plug-and-play reusable LogGP model that can be used to predict the runtime and scaling behavior of different MPI-based pipelined wavefront applications runni...
Gihan R. Mudalige, Mary K. Vernon, Stephen A. Jarv...
ITCC
2003
IEEE
15 years 9 months ago
An Open Software Architecture for Structured Data Elaboration and Transcoding
In this paper, we propose a software architecture model for the development of elaboration/transcoding modules for structured data. We define a flexible implementation approach ...
Luca Vollero, Giulio Iannello, Francesco Delfino
138
Voted
SOSP
1993
ACM
15 years 5 months ago
The Information Bus - An Architecture for Extensible Distributed Systems
Research can rarely be performed on large-scale, distributed systems at the level of thousands of workstations. In this paper, we describe the motivating constraints, design princ...
Brian M. Oki, Manfred Pflügl, Alex Siegel, Da...