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ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 1 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
TC
2008
14 years 9 months ago
High-Performance Architecture of Elliptic Curve Scalar Multiplication
A high performance architecture of elliptic curve scalar multiplication over finite field GF(2m ) is proposed. A pseudo-pipelined word serial finite field multiplier with word siz...
B. Ansari, M. A. Hasan
ICS
2004
Tsinghua U.
15 years 3 months ago
Evaluating support for global address space languages on the Cray X1
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
Christian Bell, Wei-Yu Chen, Dan Bonachea, Katheri...
TC
2010
14 years 8 months ago
Architecture Exploration of High-Performance PCs with a Solid-State Disk
—As the cost per bit of NAND flash memory devices rapidly decreases, NAND-flash-based Solid-State Disks (SSDs) are replacing Hard Disk Drives (HDDs) used in a wide spectrum of co...
Dong Kim, Kwanhu Bang, Seung-Hwan Ha, Sungroh Yoon...
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
15 years 1 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu