Sciweavers

2852 search results - page 232 / 571
» High Performance Architectures and Compilers
Sort
View
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
15 years 7 months ago
Approximation Algorithm for Process Mapping on Network Processor Architectures
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...
Christopher Ostler, Karam S. Chatha, Goran Konjevo...
ICASSP
2011
IEEE
14 years 7 months ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...
HPCA
1998
IEEE
15 years 7 months ago
Non-Stalling CounterFlow Architecture
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
15 years 5 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
115
Voted
ROBOCUP
2001
Springer
75views Robotics» more  ROBOCUP 2001»
15 years 8 months ago
A Modular Hierarchical Behavior-Based Architecture
Abstract. This paper describes a highly modular hierarchical behaviorbased control system for robots. Key features of the architecture include: easy addition/removal of behaviors, ...
Scott Lenser, James Bruce, Manuela M. Veloso