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» High Performance Architectures and Compilers
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CGO
2010
IEEE
15 years 10 months ago
Automatic creation of tile size selection models
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
Tomofumi Yuki, Lakshminarayanan Renganarayanan, Sa...
ANCS
2006
ACM
15 years 9 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...
CASES
2005
ACM
15 years 5 months ago
Architectural support for real-time task scheduling in SMT processors
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
Francisco J. Cazorla, Peter M. W. Knijnenburg, Riz...
OSDI
2002
ACM
16 years 4 months ago
Using Model Checking to Debug Device Firmware
Device firmware is a piece of concurrent software that achieves high performance at the cost of software complexity. They contain subtle race conditions that make them difficult t...
Sanjeev Kumar, Kai Li
LCTRTS
2009
Springer
15 years 10 months ago
Eliminating the call stack to save RAM
Most programming languages support a call stack in the programming model and also in the runtime system. We show that for applications targeting low-power embedded microcontroller...
Xuejun Yang, Nathan Cooprider, John Regehr