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HIPEAC
2007
Springer
15 years 10 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
ASWEC
2007
IEEE
15 years 8 months ago
Explicitly Controlling the Fair Service for Busy Web Servers
There is a growing demand for web applications to provide fair service to the highly concurrent requests. In this paper, we present an approach to addressing this requirement. Bas...
Zhanwen Li, David Levy, Shiping Chen, John Zic
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
16 years 4 months ago
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
INFOCOM
2003
IEEE
15 years 9 months ago
Distributed Admission Control to Support Guaranteed Services in Core-Stateless Networks
— The core-stateless service architecture alleviates the scalability problems of the integrated service framework while maintaining its guaranteed service semantics. The admissio...
Sudeept Bhatnagar, B. R. Badrinath
ARC
2006
Springer
157views Hardware» more  ARC 2006»
15 years 7 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...