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ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
15 years 9 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
REFLECTION
2001
Springer
15 years 8 months ago
Performance and Integrity in the OpenORB Reflective Middleware
, are to address what we perceive as the most pressing shortcomings of current reflective middleware platforms. First, performance: in the worst case, this needs to be on a par wit...
Gordon S. Blair, Geoff Coulson, Michael Clarke, Ni...
142
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HPCA
2000
IEEE
15 years 8 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
15 years 10 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
ISPASS
2003
IEEE
15 years 9 months ago
Performance study of a cluster runtime system for dynamic interactive stream-oriented applications
Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism, and high computational requirements, making ...
Arnab Paul, Nissim Harel, Sameer Adhikari, Bikash ...