2852 search results - page 266 / 571 » High Performance Architectures and Compilers |
174
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ANCS
2011
ACM
14 years 4 months ago
2011
ACM
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
156
Voted
CSMR
2004
IEEE
15 years 7 months ago
2004
IEEE
Combining static and dynamic information is highly relevant in many reverse engineering, program comprehension and maintenance task. Dynamic analysis is particularly effective whe...
132
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ISPASS
2006
IEEE
15 years 10 months ago
2006
IEEE
The present work presents a cycle-level execution-driven simulator for modern GPU architectures. We discuss the simulation model used for our GPU simulator, based in the concept o...
147
Voted
TCSV
2008
15 years 4 months ago
2008
Abstract--In contrast to the macroblock-based in-loop deblocking filters, the filters of VC-1 perform all horizontal edges (for in-loop filtering) or vertical edges (for overlap sm...
132
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SOSP
2001
ACM
16 years 28 days ago
2001
ACM
We propose a new design for highly concurrent Internet services, which we call the staged event-driven architecture (SEDA). SEDA is intended to support massive concurrency demands...