Sciweavers

2852 search results - page 267 / 571
» High Performance Architectures and Compilers
Sort
View
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
15 years 10 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
COMCOM
2007
111views more  COMCOM 2007»
15 years 4 months ago
Failover, load sharing and server architecture in SIP telephony
We apply some of the existing web server redundancy techniques for high service availability and scalability to the relatively new IP telephony context. The paper compares various...
Kundan Singh, Henning Schulzrinne
ICIP
2006
IEEE
16 years 5 months ago
FPGA Architecture for Real-Time Video Noise Estimation
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
Francois-Xavier Lapalme, Aishy Amer, Chunyan Wang
ICCD
2007
IEEE
146views Hardware» more  ICCD 2007»
16 years 1 months ago
Exploring DRAM cache architectures for CMP server platforms
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald New...