Sciweavers

2852 search results - page 288 / 571
» High Performance Architectures and Compilers
Sort
View
IWMM
2009
Springer
114views Hardware» more  IWMM 2009»
15 years 10 months ago
Scalable support for multithreaded applications on dynamic binary instrumentation systems
Dynamic binary instrumentation systems are used to inject or modify arbitrary instructions in existing binary applications; several such systems have been developed over the past ...
Kim M. Hazelwood, Greg Lueck, Robert Cohn
EMSOFT
2004
Springer
15 years 9 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
Kun Zhang, Tao Zhang, Santosh Pande
CNSR
2008
IEEE
140views Communications» more  CNSR 2008»
15 years 10 months ago
An Approach for Optimal Bandwidth Allocation in Packet Processing Systems
The increasing demand for more bandwidth and the increased application variety fuel the need for high performance network processors. A simple but highly repetitive task performed...
Mahmood Ahmadi, Stephan Wong
CASES
2008
ACM
15 years 6 months ago
Efficient vectorization of SIMD programs with non-aligned and irregular data access hardware
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...
Hoseok Chang, Wonyong Sung
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 9 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...