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MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 8 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 9 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
CODES
2008
IEEE
15 years 6 months ago
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting...
Christos Strydis, Georgi Gaydadjiev
JCM
2008
118views more  JCM 2008»
15 years 4 months ago
New Receiver Architecture Based on Optical Parallel Interference Cancellation for the Optical CDMA
Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system,...
N. Elfadel, A. A. Aziz, E. Idriss, A. Mohammed, N....
ASPLOS
2009
ACM
16 years 4 months ago
Producing wrong data without doing anything obviously wrong!
This paper presents a surprising result: changing a seemingly innocuous aspect of an experimental setup can cause a systems researcher to draw wrong conclusions from an experiment...
Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Pe...