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CASES
2009
ACM
15 years 8 months ago
Exploiting residue number system for power-efficient digital signal processing in embedded processors
2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propaga...
Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shr...
ICCD
2002
IEEE
114views Hardware» more  ICCD 2002»
16 years 1 months ago
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Che...
FPL
2004
Springer
128views Hardware» more  FPL 2004»
15 years 9 months ago
Design and Implementation of a CFAR Processor for Target Detection
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
Cesar Torres-Huitzil, René Cumplido-Parra, ...
ISCA
1998
IEEE
128views Hardware» more  ISCA 1998»
15 years 8 months ago
Analytic Evaluation of Shared-memory Systems with ILP Processors
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mar...
ERSA
2004
148views Hardware» more  ERSA 2004»
15 years 5 months ago
Efficient Floating-point Based Block LU Decomposition on FPGAs
In this paper, we propose an architecture for floatingpoint based LU decomposition for large-sized matrices. Our proposed architecture is based on the well known concept of blocki...
Gokul Govindu, Viktor K. Prasanna, Vikash Daga, Sr...