2852 search results - page 325 / 571 » High Performance Architectures and Compilers |
127
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JFR
2006
15 years 4 months ago
2006
This paper describes the implementation and testing of Alice, the California Institute of Technology's entry in the 2005 DARPA Grand Challenge. Alice utilizes a highly networ...
140
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FPL
2008
Springer
15 years 6 months ago
2008
Springer
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
134
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ISCAPDCS
2003
15 years 5 months ago
2003
We consider efficient strategies for the parallel and distributed computation of large sets of multivariate integrals. These arise in many applications such as computational chem...
124
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MJ
2008
15 years 4 months ago
2008
This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reco...
122
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CCGRID
2001
IEEE
15 years 8 months ago
2001
IEEE
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of high performance of VIA, the previous MPI implementati...