Sciweavers

2852 search results - page 340 / 571
» High Performance Architectures and Compilers
Sort
View
TCAD
2002
118views more  TCAD 2002»
15 years 4 months ago
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo ...
141
Voted
USS
2010
15 years 2 months ago
Cling: A Memory Allocator to Mitigate Dangling Pointers
Use-after-free vulnerabilities exploiting so-called dangling pointers to deallocated objects are just as dangerous as buffer overflows: they may enable arbitrary code execution. U...
Periklis Akritidis
MICRO
2006
IEEE
191views Hardware» more  MICRO 2006»
15 years 4 months ago
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
Pierre Palatin, Yves Lhuillier, Olivier Temam
ICS
2009
Tsinghua U.
15 years 11 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell
IPPS
2008
IEEE
15 years 11 months ago
Financial modeling on the cell broadband engine
High performance computing is critical for financial markets where analysts seek to accelerate complex optimizations such as pricing engines to maintain a competitive edge. In th...
Virat Agarwal, Lurng-Kuo Liu, David A. Bader