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ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
15 years 11 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
APCSAC
2005
IEEE
15 years 10 months ago
The Challenges of Massive On-Chip Concurrency
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...
Kostas Bousias, Chris R. Jesshope
WICON
2008
15 years 6 months ago
A network mobility management scheme for fast QoS handover
The evolution of wireless access technologies has led to a new era of Mobile Internet. Network mobility, which considers the mobility of an entire network, is particularly suitabl...
Cheng-Wei Lee, Meng Chang Chen, Yeali S. Sun
164
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IPPS
2010
IEEE
15 years 2 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
15 years 11 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...