2852 search results - page 362 / 571 » High Performance Architectures and Compilers |
150
Voted
ADT
2005
15 years 4 months ago
2005
: The main problem concerning the hardware implementation of turbo codes is the lack of parallelism in the MAP-based decoding algorithm. This paper proposes to overcome this proble...
160
Voted
DAC
1999
ACM
16 years 5 months ago
1999
ACM
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
127
Voted
DATE
2008
IEEE
15 years 11 months ago
2008
IEEE
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
122
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ARC
2009
Springer
15 years 9 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
121
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FPL
2001
Springer
15 years 9 months ago
2001
Springer
Although FPGA technology offers the potential of designing high performance systems at low cost, its programming model is prohibitively low level. To allow a novice signal/image pr...