2852 search results - page 36 / 571 » High Performance Architectures and Compilers |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in t...
ICPPW
2005
IEEE
15 years 3 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
POS
1998
Springer
15 years 2 months ago
1998
Springer
This paper argues that caching, atomicity and layering are fundamental to persistent systems, and that the transactional object cache architecture, as an embodiment of these conce...
APCSAC
2001
IEEE
15 years 1 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...