2852 search results - page 376 / 571 » High Performance Architectures and Compilers |
144
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ICRA
2009
IEEE
15 years 2 months ago
2009
IEEE
In previous studies on 4-DOF parallel mechanisms with four sub-chains, only symmetric arrangement of those four chains connected to the top plate was considered. Such symmetric sha...
149
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DDECS
2009
IEEE
15 years 11 months ago
2009
IEEE
—Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing...
157
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CASES
2009
ACM
15 years 11 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
174
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ISM
2005
IEEE
15 years 10 months ago
2005
IEEE
The new IP Multimedia Subsystem (IMS) provides an overlay architecture for IP based core networks and enables the efficient provision of an open set of potentially highly integrat...
143
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DAC
2003
ACM
15 years 10 months ago
2003
ACM
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...