2852 search results - page 382 / 571 » High Performance Architectures and Compilers |
138
click to vote
FPL
1997
Springer
15 years 9 months ago
1997
Springer
Protocol Boosters are functional elements, inserted anddeleted fromnetwork protocol stacks on an as-neededbasis. The Protocol Booster design methodology attempts to improve end-to-...
147
click to vote
FCCM
2009
IEEE
15 years 8 months ago
2009
IEEE
This paper proposes a high performance least square solver on FPGAs using the Cholesky decomposition method. Our design can be realized by iteratively adopting a single triangular...
136
Voted
CATA
2004
15 years 6 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
112
click to vote
TOMS
2011
14 years 11 months ago
2011
We present a new supernode-based incomplete LU factorization method to construct a preconditioner for solving sparse linear systems with iterative methods. The new algorithm is pr...
138
click to vote
DAC
2008
ACM
16 years 5 months ago
2008
ACM
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...