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IEEEPACT
2005
IEEE
15 years 10 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
ISCAPDCS
2003
15 years 6 months ago
Efficient Data Allocation for a Cluster of Workstations
The development and use of cluster based computing is increasingly becoming an effective approach for solving high performance computing problems. The trend of moving away from sp...
Ahmed M. Mohamed, Reda A. Ammar, Lester Lipsky
DAC
2007
ACM
16 years 6 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
HPCA
2001
IEEE
16 years 5 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
ISCA
2008
IEEE
125views Hardware» more  ISCA 2008»
15 years 11 months ago
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H....