Sciweavers

2852 search results - page 410 / 571
» High Performance Architectures and Compilers
Sort
View
116
Voted
ICPP
2006
IEEE
15 years 11 months ago
Vector Lane Threading
Multi-lane vector processors achieve excellent computational throughput for programs with high data-level parallelism (DLP). However, application phases without significant DLP ar...
Suzanne Rivoire, Rebecca Schultz, Tomofumi Okuda, ...
ISCAS
2006
IEEE
163views Hardware» more  ISCAS 2006»
15 years 11 months ago
ASIC hardware implementation of the IDEA NXT encryption algorithm
— Symmetric-key block ciphers are often used to provide data confidentiality with low complexity, especially in the case of dedicated hardware implementations. IDEA NXT is a nov...
Marco Macchetti, Wenyu Chen
156
Voted
ISCAS
2006
IEEE
124views Hardware» more  ISCAS 2006»
15 years 11 months ago
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4
Abstract— There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in th...
Alexandros Bartzas, Miguel Peón Quiró...
RTAS
2006
IEEE
15 years 11 months ago
Adaptive Allocation of Software and Hardware Real-Time Tasks for FPGA-based Embedded Systems
Operating systems for reconfigurable devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a recon...
Rodolfo Pellizzoni, Marco Caccamo
144
Voted
MOBICOM
2006
ACM
15 years 11 months ago
Video streaming over overlaid bluetooth piconets (OBP)
In a large scale Bluetooth network, scatternet has been regarded as the only interconnection method among piconets. But, most Bluetooth devices do not support scatternet connectio...
Sewook Jung, Alexander Chang, Mario Gerla