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MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
15 years 4 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
IJPP
2011
105views more  IJPP 2011»
15 years 1 months ago
Correlating Radio Astronomy Signals with Many-Core Hardware
A recent development in radio astronomy is to replace traditional dishes with many small antennas. The signals are combined to form one large, virtual telescope. The enormous data ...
Rob van Nieuwpoort, John W. Romein
IPPS
2005
IEEE
15 years 11 months ago
Predicting Cache Space Contention in Utility Computing Servers
The need to provide performance guarantee in high performance servers has long been neglected. Providing performance guarantee in current and future servers is difficult because ï...
Yan Solihin, Fei Guo, Seongbeom Kim
ANCS
2006
ACM
15 years 10 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo

Publication
767views
17 years 4 months ago
Analysis of the Increase/Decrease Algorithms for Congestion Avoidance in Computer Networks
Congestion avoidance mechanisms allow a network to operate in the optimal region of low delay and high throughput, thereby, preventing the network from becoming congested. This is ...
D. Chiu and R. Jain