2852 search results - page 45 / 571 » High Performance Architectures and Compilers |
DSD
2010
IEEE
14 years 10 months ago
2010
IEEE
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
DAC
1994
ACM
15 years 2 months ago
1994
ACM
Abstract -- This paper describes a new memory estimation technique for DSP applications written in an applicative language. Since no concept of storage is present in an applicative...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
116
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VEE
2005
ACM
15 years 3 months ago
2005
ACM
We present an optimized implementation of the linear scan register allocation algorithm for Sun Microsystems’ Java HotSpotTM client compiler. Linear scan register allocation is ...
148
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DATE
2011
IEEE
14 years 1 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...