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» High Performance Architectures and Compilers
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HIPC
1999
Springer
15 years 2 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
VLSISP
2008
159views more  VLSISP 2008»
14 years 9 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
ICS
1997
Tsinghua U.
15 years 2 months ago
Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology
Modern microprocessors can achieve high performance on linear algebra kernels but this currently requires extensive machine-speci c hand tuning. We have developed a methodology wh...
Jeff Bilmes, Krste Asanovic, Chee-Whye Chin, James...
DAC
2002
ACM
15 years 11 months ago
A universal technique for fast and flexible instruction-set architecture simulation
In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance ...
Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rain...
TPDS
2010
144views more  TPDS 2010»
14 years 8 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee