2852 search results - page 70 / 571 » High Performance Architectures and Compilers |
AUTOID
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, amo...
DAC
2005
ACM
14 years 12 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
PLDI
2010
ACM
15 years 3 months ago
2010
ACM
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
CCGRID
2006
IEEE
15 years 1 months ago
2006
IEEE
MPICH2 provides a layered architecture for implementing MPI-2. In this paper, we provide a new design for implementing MPI-2 over InfiniBand by extending the MPICH2 ADI3 layer. Ou...
IJSNET
2007
14 years 9 months ago
2007
: This paper describes the implementation architecture and performance analysis of nanoMAC, a CSMA/CA based medium access control protocol, which is specifically designed for high...