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ICASSP
2008
IEEE
15 years 9 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
IFL
2001
Springer
142views Formal Methods» more  IFL 2001»
15 years 7 months ago
A Compilation Scheme for a Hierarchy of Array Types
In order to achieve a high level of abstraction, array-oriented languages provide language constructs for defining array operations in a shape-invariant way. However, when trying ...
Dietmar Kreye
ICCD
2004
IEEE
123views Hardware» more  ICCD 2004»
16 years 4 hour ago
Compiler-Based Frame Formation for Static Optimization
We selectively generate and optimize the frames constructed by the rePLay architecture statically. Since static analysis provides a global view of the interaction between the basi...
Feng Shi, Sobeeh Almukhaizim, Pey-Chang Lin, Yiorg...
FPL
2008
Springer
150views Hardware» more  FPL 2008»
15 years 4 months ago
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs
Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computat...
Betul Buyukkurt, Walid A. Najjar
PLDI
2012
ACM
13 years 5 months ago
Adaptive input-aware compilation for graphics engines
While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required...
Mehrzad Samadi, Amir Hormati, Mojtaba Mehrara, Jan...