Sciweavers

2852 search results - page 94 / 571
» High Performance Architectures and Compilers
Sort
View
IPPS
1998
IEEE
15 years 7 months ago
Compiler-Optimization of Implicit Reductions for Distributed Memory Multiprocessors
This paper presents reduction recognition and parallel code generationstrategies for distributed-memorymultiprocessors. We describe techniques to recognize a broad range of implic...
Bo Lu, John M. Mellor-Crummey
FPL
2003
Springer
259views Hardware» more  FPL 2003»
15 years 8 months ago
Branch Optimisation Techniques for Hardware Compilation
Abstract. This paper explores using information about program branch probabilities to optimise reconfigurable designs. The basic premise is to promote utilization by dedicating mo...
Henry Styles, Wayne Luk
PPOPP
2005
ACM
15 years 8 months ago
Fault tolerant high performance computing by a coding approach
As the number of processors in today’s high performance computers continues to grow, the mean-time-to-failure of these computers are becoming significantly shorter than the exe...
Zizhong Chen, Graham E. Fagg, Edgar Gabriel, Julie...
ICS
2005
Tsinghua U.
15 years 8 months ago
High performance support of parallel virtual file system (PVFS2) over Quadrics
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...
Weikuan Yu, Shuang Liang, Dhabaleswar K. Panda
ANCS
2005
ACM
15 years 8 months ago
Segmented hash: an efficient hash table implementation for high performance networking subsystems
Hash tables provide efficient table implementations, achieving O(1), query, insert and delete operations at low loads. However, at moderate or high loads collisions are quite freq...
Sailesh Kumar, Patrick Crowley