205 search results - page 14 / 41 » High Performance Array Processor for Video Decoding |
113
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MTPP
2010
14 years 6 months ago
2010
The ubiquity of many-core architectures poses challenges to software developers to make scalable software. To parallelize data-intensive applications on a many-core platform, one h...
ITCC
2003
IEEE
15 years 5 months ago
2003
IEEE
In this paper, we propose a software architecture model for the development of elaboration/transcoding modules for structured data. We define a flexible implementation approach ...
ISVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
ISSS
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
118
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TVLSI
2008
14 years 11 months ago
2008
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...