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» High Performance Array Processor for Video Decoding
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VLSISP
2010
102views more  VLSISP 2010»
15 years 1 days ago
A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems
Fine-grained accelerators have the potential to deliver significant benefits in various platforms for embedded signal processing. Due to the moderate complexity of their targeted o...
Jani Boutellier, Shuvra S. Bhattacharyya, Olli Sil...
RSP
2008
IEEE
182views Control Systems» more  RSP 2008»
15 years 8 months ago
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
ICMCS
2006
IEEE
130views Multimedia» more  ICMCS 2006»
15 years 7 months ago
Video Analysis and Compression on the STI Cell Broadband Engine Processor
With increased concern for physical security, video surveillance is becoming an important business area. Similar camera-based system can also be used in such diverse applications ...
Lurng-Kuo Liu, Sreeni Kesavarapu, Jonathan Connell...
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
16 years 2 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
VCIP
2003
140views Communications» more  VCIP 2003»
15 years 3 months ago
Error-resilient performance evaluation of MPEG-4 and H.264
Recent advances in video coding technology have resulted in rapid growth of application in mobile communication. With this explosive growth, reliable transmission and error resili...
Bongsoo Jung, Younghooi Hwang, Byeungwoo Jeon, Myu...