205 search results - page 17 / 41 » High Performance Array Processor for Video Decoding |
VLSISP
2008
14 years 11 months ago
2008
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
100
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FPL
2004
Springer
15 years 5 months ago
2004
Springer
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
In this paper, we show the necessity of reconfigurable hardware for data and signal processing in wireless mobile terminals. We first identify the key processing power requirement...
121
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IPPS
2005
IEEE
15 years 5 months ago
2005
IEEE
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
CODES
2005
IEEE
15 years 1 months ago
2005
IEEE
We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application’s binary are competitive with parti...