205 search results - page 18 / 41 » High Performance Array Processor for Video Decoding |
VTC
2010
IEEE
14 years 10 months ago
2010
IEEE
— In this contribution we propose a robust H.264 coded wireless video transmission scheme using iteratively decoded self-concatenated convolutional coding (SECCC). The proposed S...
119
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CODES
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
ICASSP
2009
IEEE
15 years 6 months ago
2009
IEEE
Motion scalability is designed to improve the coding efficiency of a scalable video coding framework, especially in the medium to low range of decoding bit rates or spatial resol...
120
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DAC
2000
ACM
16 years 22 days ago
2000
ACM
In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications...
DAC
2002
ACM
16 years 22 days ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...