205 search results - page 27 / 41 » High Performance Array Processor for Video Decoding |
118
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ICC
2007
IEEE
15 years 8 months ago
2007
IEEE
—In this paper, we present an original image quality metric for open-loop transcoding architectures based on frequency selective transmission. The proposed metric computes the no...
102
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ICASSP
2011
IEEE
14 years 5 months ago
2011
IEEE
Error resilient video coding critically relies on the accuracy of endto-end distortion estimation. An established solution, the recursive optimal per-pixel estimate (ROPE), is bas...
123
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ESTIMEDIA
2009
Springer
15 years 8 months ago
2009
Springer
—We have integrated processing with deterministic and non-deterministic resource usage in an overall application and evaluated its performance on a multi-core processor platform....
102
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HPCA
2008
IEEE
16 years 2 months ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
115
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DAC
2002
ACM
16 years 2 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...