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» High Performance Array Processor for Video Decoding
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ICIP
2004
IEEE
16 years 1 months ago
Drift reduction for a H.264/AVC fine grain scalability with motion compensation architecture
The recent advances in non-scalable video encoding brought by the H.264/AVC standard offered significant improvements in terms of rate-distortion performance. This paper proposes ...
João Ascenso, Fernando Pereira
IPPS
2006
IEEE
15 years 5 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
SIGMETRICS
2005
ACM
127views Hardware» more  SIGMETRICS 2005»
15 years 5 months ago
A data streaming algorithm for estimating subpopulation flow size distribution
Statistical information about the flow sizes in the traffic passing through a network link helps a network operator to characterize network resource usage, infer traffic demands,...
Abhishek Kumar, Minho Sung, Jun Xu, Ellen W. Zegur...
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
15 years 4 months ago
CMOS system-on-a-chip voltage scaling beyond 50nm
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoo...
106
Voted
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 3 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...