205 search results - page 5 / 41 » High Performance Array Processor for Video Decoding |
90
Voted
MVA
1992
15 years 25 days ago
1992
This study reports on the performance of a Real-Time Vision System (RVS) and its use of an IMAP prototype LSI. This LSI integrates eight 8 bit processors and a 144 Kbit SRAM on a ...
120
Voted
FPL
2006
Springer
15 years 3 months ago
2006
Springer
A field-programmable gate array (FPGA) implementation of a new detection algorithm for uncoded multiple inputmultiple output (MIMO) systems based on the complex version of the sph...
77
Voted
SIPS
2006
IEEE
15 years 5 months ago
2006
IEEE
Although many stopping methods of iterative decoding have been discussed in the literatures extensively, many of them only focus on the solvable decoding. In this paper, we propos...
HIPEAC
2009
Springer
15 years 6 months ago
2009
Springer
In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inte...
105
Voted
ISCAS
2008
IEEE
15 years 6 months ago
2008
IEEE
— In this paper an analysis of bi-dimensional video filtering on the Cell Broadband Engine Processor is presented. To evaluate the processor, a highly adaptive filtering algori...