205 search results - page 6 / 41 » High Performance Array Processor for Video Decoding |
85
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibil...
ISVLSI
2005
IEEE
15 years 5 months ago
2005
IEEE
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate...
ICCD
2002
IEEE
15 years 8 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
VLSISP
2008
14 years 11 months ago
2008
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
DAC
2011
ACM
13 years 11 months ago
2011
ACM
A three-dimensional (3D) CMOS imager constructed from stacking a pixel array of image sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) arra...