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» High Performance Array Processor for Video Decoding
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CORR
2006
Springer
103views Education» more  CORR 2006»
14 years 11 months ago
VXA: A Virtual Architecture for Durable Compressed Archives
Data compression algorithms change frequently, and obsolete decoders do not always run on new hardware and operating systems, threatening the long-term usability of content archiv...
Bryan Ford
DATE
2008
IEEE
217views Hardware» more  DATE 2008»
15 years 6 months ago
A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio
The Software-Defined Radio (SDR) concept aims to enabling costeffective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication ...
Bruno Bougard, Bjorn De Sutter, Sebastien Rabou, D...
DAC
1999
ACM
16 years 20 days ago
CAD Directions for High Performance Asynchronous Circuits
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi...
ICMCS
1999
IEEE
150views Multimedia» more  ICMCS 1999»
15 years 4 months ago
DIVeR: A Dynamic Interactive Video Retrieval Protocol for Disk Array Based Servers
Video-on-demand (VOD) is a very promising multimedia application of the near future. In order for such a service to be commercially viable, efficient storage and retrieval schemes...
Senthil Sengodan, Victor O. K. Li
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...