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» High Performance Array Processor for Video Decoding
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SPAA
1996
ACM
15 years 3 months ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
ICIP
2000
IEEE
16 years 1 months ago
Performance Analysis of an H.263 Video Encoder for VIRAM
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
Thinh P. Q. Nguyen, Avideh Zakhor, Katherine A. Ye...
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 5 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ICIP
2009
IEEE
16 years 22 days ago
A High Throughput Cabac Algorithm Using Syntax Element Partitioning
Enabling parallel processing is becoming increasingly necessary for video decoding as performance requirements continue to rise due to growing resolution and frame rate demands. I...
ICMCS
2008
IEEE
336views Multimedia» more  ICMCS 2008»
15 years 6 months ago
SIMD optimization of the H.264/SVC decoder with efficient data structure
H.264/scalable video coding (SVC) is a new compression technique that can adapt to various network environments and applications. However, despite its outstanding performance, H.2...
Joohyun Lee, Gwanggil Jeon, Sangjun Park, Taeyoung...