12055 search results - page 10 / 2411 » High Performance Banking |
ICPR
2004
IEEE
15 years 10 months ago
2004
IEEE
A methodology using decoder banks is proposed for high-accuracy, fully automatic recognition of machine printed text across a wide range of challenging image qualities, without re...
102
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WMPI
2004
ACM
15 years 3 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
68
Voted
ICASSP
2007
IEEE
15 years 4 months ago
2007
IEEE
When an oversampled FIR filter bank structure is used for signal analysis, a main problem is to guarantee its invertibility and to be able to determine an inverse synthesis filt...
79
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
105
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FPGA
2004
ACM
15 years 3 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...