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ISVLSI
2007
IEEE
100views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Vector Processing Support for FPGA-Oriented High Performance Applications
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor suppor...
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie...
HIPEAC
2007
Springer
15 years 10 months ago
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
Major Bhadauria, Sally A. McKee, Karan Singh, Gary...
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
15 years 10 months ago
High performance error concealment algorithm by motion vector refinement for MPEG-4 video
—In this paper, a new error concealment algorithm by recursive motion vector refinement is proposed. The proposed method utilizes the top/bottom motion vectors of lost MB in curr...
Ming-Chieh Chi, Mei-Juan Chen, Jia-Hwa Liu, Ching-...
HIPEAC
2005
Springer
15 years 10 months ago
Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multila...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
ISVLSI
2003
IEEE
115views VLSI» more  ISVLSI 2003»
15 years 9 months ago
Getting High-Performance Silicon from System-Level Design
System-level design techniques promise a way to lessen the productivity gap between fabrication and design. Unfortunately, these techniques have been slow to catch on, in part bec...
W. Rhett Davis