12055 search results - page 203 / 2411 » High Performance Banking |
128
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SCOPES
2005
Springer
15 years 10 months ago
2005
Springer
The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access ...
153
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FPL
2006
Springer
15 years 8 months ago
2006
Springer
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
127
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CONCURRENCY
2006
15 years 5 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
154
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JMLR
2012
13 years 7 months ago
2012
We study sparse principal components analysis in the high-dimensional setting, where p (the number of variables) can be much larger than n (the number of observations). We prove o...
163
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HPCA
2009
IEEE
16 years 5 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...